1. Field of the Invention
The present invention relates to a pseudo-random pattern generating circuit (hereinafter referred to as "PN pattern generating circuit"), and in particular to a PN pattern generating circuit which is capable of designating a plurality of PN stages, and outputting pseudo-random patterns for multiplexing (hereinafter referred to as "multiplex PN patterns") of a plurality of PN stages.
2. Relevant Art
FIG. 4 is a diagram showing a structure of a conventional PN pattern generating circuit. This circuit is a PN pattern generating circuit for multiplexing and is constructed from D-type flip-flop circuits (hereinafter referred to as "DFF circuits") 1-1.about.1-M, N:1 select circuits 10-1.about.10-M, multiplex PN pattern arithmetic circuits 11-1.about.11-N, etc. Furthermore, in FIG. 4, PN stage selection signal input terminal 5, multiplex PN pattern signal output terminal 6, and clock input terminal 7 are also provided.
Multiplex PN pattern arithmetic circuits 11-1.about.11-N are arithmetic circuits for use in different PN stages which input the output of DFF circuits 1-1.about.1-M, and compute and output the multiplex PN pattern of the subsequent time instant. In addition, select circuits 10-1.about.10-M select the output of multiplex PN pattern arithmetic circuits 11-1.about.11-N by means of the PN stage selection signal from PN stage selection signal input terminal 5. Furthermore, DFF circuits 1-1.about.1-M conduct re-timing of the outputs of N:1 select circuits 10-1.about.10-M, and output multiplex PN pattern signal.
FIG. 5 is a diagram showing an example of a PN pattern generating circuit which outputs a PN pattern of a single PN stage which is not for multiplexing. The PN pattern generating circuit shown in FIG. 5 is constructed from shift register comprising DFF circuits 42-1.about.42-N of n stages, and exclusive OR arithmetic circuit 43 which forms the feedback input thereof. Furthermore, in FIG. 5, a clock input terminal 40 and PN pattern output terminal 41 are also provided.
In addition, as shown in the aforementioned Figure, a respective character is assigned to each of DFF circuits 42-1.about.42-n beginning from the PN pattern output terminal 41 side, i.e., 1, 2, 3, . . . , i, . . . , m, n, and the output of the jth DFF circuit of a certain instant t is expressed by Qj(t). In this manner, since the shift register is formed from DFF circuits 42-1.about.42-n, output Qj(t+1) of jth DFF circuit at time instant (t+1) following one clock input to DFF circuits 42-1.about.42-n via clock input terminal 40 is expressed by the following Formula (1). Here, j.ltoreq.m.
Formula (1) EQU Qj(t+1)=Qj+1(t)
In addition, the output of the nth DFF circuit 42-n at time instant t+1 is the exclusive OR of the 1st DFF circuit 42-1 and ith DFF circuit 42-i, and is hence expressed by the following Formula (2). Furthermore, "*" is the computation (arithmetic) conducted by means of exclusive OR arithmetic circuit 43.
Formula (2) EQU Qn(t+1)=Q1(t)*Qi(t)
Consequently, the PN pattern, Q1(t), Q1(t+1), Q1(t+2), . . . , is sequentially outputted from PN pattern output terminal 41. Accordingly, the PN pattern possesses a certain cycle. This cycle is determined by means of the stages n of the shift register and specifically comprises a (2n-1) clock. In this manner, the stages n of this shift register is referred to as "PN stage".
As a method for low-cost, high-speed output of PN patterns, methods are known in which the parallel PN pattern is outputted, or in which PN patterns are multiplexed using a multiplexing circuit which operates at an even higher speed and then outputted. The circuit for generating parallel PN patterns for this multiplexing is a multiplex PN pattern generating circuit, and the data outputted from this circuit corresponds to multiplex PN patterns. For example, a PN pattern generating circuit for M-multiplexing is constructed by means of M number of DFF circuits.
Thus, in order to prepare a data sequence formed from the aforementioned PN patterns Q1(t), Q1(t+1), . . . , for multiplexing, it is unnecessary to output in parallel this data sequence. If the number of PN patterns required for M-multiplexing is designated as "M", then the required data sequence is as follows.
Formula (3) ##EQU1##
These data sequences can be rewritten in the following manner by means of the aforementioned Formula (1), and thus a circuit is required for computing the states of each DFF circuit M clocks ahead.
Formula (4) ##EQU2##
As an example of a circuit for computing the aforementioned state, an 8-multiplex PN pattern arithmetic circuit comprising seven stages is shown in FIG. 6. This circuit is constructed using exclusive OR arithmetic circuits 30-1 .about.30-8. The output of DFF circuit is fed back and inputted into terminals 32-1 .about.32-7 and the arithmetic results for the subsequent states of each DFF circuit are outputted from terminals 31-1.about.31-8.
FIG. 6 shows an example of a multiplex PN pattern arithmetic circuit comprising seven stages; when outputting other PN stages, a different PN pattern arithmetic circuit is required, however, the case of multiplex PN pattern arithmetic circuits for multiplexing other PN stages is similar and can be formed using only multiple-input exclusive OR arithmetic circuits. According to the conventional PN pattern generating circuit for outputting a plurality of PN stages, a structure was realized comprising a plurality of PN pattern arithmetic circuits for multiplexing wherein PN stage switching was conducted by means of switching the output therefrom using a select circuit.
For example, the PN pattern generating circuit shown in FIG. 4 outputs PN patterns of N types of PN stages and comprises N number of PN pattern arithmetic circuits 11-1.about.11-N. The outputs of these N number of PN pattern arithmetic circuits 11-1.about.11-N undergo PN stage switching in N:1 select circuits 10-1.about.10-M using the PN stage selection signals from PN stage selection signal input terminal 5.
In the conventional PN pattern generating circuit for outputting a plurality of PN stages, PN pattern arithmetic circuits corresponding to the number of PN stages to be outputted were provided, and the outputs of these PN pattern arithmetic circuits were switched by means of a select circuit such that the output of a plurality of PN stage patterns was possible.
However, according to the structure of this conventional PN pattern generating circuit, the number of PN pattern arithmetic circuits must be proportional to the number of PN stages to be outputted, and as a result, the gate scale is increased, thereby increasing the circuit scale as well. In addition, the fan-out of each DFF circuit is the overall sum of the fan-ins of each PN pattern arithmetic circuit. Thus, this value increases in proportion with the number of PN pattern arithmetic circuits. As a result, in consideration of the signal delay between DFF circuit and PN pattern arithmetic circuit, a buffer or the like must be inserted thereinbetween.
However, due to the addition of this buffer, high speed operation of PN pattern generating circuits is hindered according to the conventional PN pattern generating circuit.